Metodologia para síntese automática de máquinas de estados finitos baseada em descrição em alto nível de abstração

Abstract

This paper present a methodology of synthesis of descriptions in high-level of abstraction for finite state machines. The synthesis process has a tools collection to perform the simulation, the reading the relevant instructions, the conversion of this instructions, the minimization and the generation of code and hardware implementation. To evaluate the methodology was used the line code HDB1 as case study. The results were obtained a minimum circuit of low cost.

Index Terms - Automatic code generation, high-level of abstraction, minimization, translation tools, finite state machine.